1. Field of the Invention
The present invention relates to a thermal process method in the field of semiconductor technology and, more particularly, to an impurity-activating thermal process method after impurity introduction.
2. Description of the Background Art
In recent years, devices have been downsized along with the increase in the degree of integration, functionality and speed of semiconductor integrated circuit devices. Accordingly, progress has been made not only with lateral miniaturization, e.g., a reduced gate length of a transistor, but also with vertical miniaturization, e.g., an ultra-thin gate insulating film. Particularly, in a transistor, the impurity diffusion in the lateral direction (channel direction) from a source/drain region and an extension region into a channel region and the impurity diffusion in the depth direction are severely restricted. This is because the short channel effect deteriorates if the impurity diffusion length in the channel direction of a transistor and the impurity diffusion depth in the depth direction thereof increase. On the other hand, there is also a demand for a reduction in resistance of these extension and source/drain regions, with the impurity diffusion length and the impurity diffusion depth being suppressed. This is because if the resistance of the extension region is reduced, the parasitic resistance from the source/drain region to the channel region is reduced, thereby obtaining a higher drive power.
Thus, there is a demand for the extension region to have a reduced resistance while suppressing the impurity diffusion length. While increasing the impurity concentration and performing a thermal process adequately are effective for obtaining a low resistance, they also lead to an increase in the impurity diffusion length. Therefore, the reduction in the diffusion length of the extension region and the reduction in the resistance thereof are in a trade-off relationship.
In order to solve this problem, an impurity introduction step employs a method in which the ion implantation energy is set to a very low level of 1 keV or less to thereby suppress the impurity introduction depth in a conventional impurity introduction process using an ion implantation method. As to the thermal process step (impurity-activating thermal process step), high-temperature, short annealing based on RTP (Rapid Thermal Processing) has been employed, instead of conventional long annealing using an electric furnace, as a way to improve the activation rate while suppressing the diffusion length. Particularly, in recent years, the impurity-activating thermal process step has been performed by a high-temperature, very short annealing called a “spike RTA”, wherein the temperature-increasing/decreasing rate (Δt) is set to about 100 to 250° C./sec (500° C./sec or less), and the holding period (the thermal process time t) for which the temperature is held at the thermal process temperature (the target temperature being 1000 to 1200° C. in practice) is set to 0 sec (50 msec to 1 sec in practice). FIG. 13A shows an example of a temperature sequence in spike RTA. In spike RTA, the target temperature is set to be high to thereby improve the impurity activation rate and to thus reduce the resistance value, while the thermal process time is set to a very short period of time of 1 sec or less to thereby suppress the impurity diffusion.
With recent very small devices, however, it is difficult, even with spike RTA, to improve the activation rate while suppressing the impurity diffusion. Specifically, while a thermal process at a higher temperature is required for improving the activation rate, it is not possible to sufficiently suppress the impurity diffusion with the thermal process time being on the order of 10 to 100 msec in spike RTA.
Therefore, millisecond annealing has recently been drawing attention instead of spike RTA. FIG. 13B shows an example of a temperature sequence in millisecond annealing. As shown in FIG. 13B, in millisecond annealing, the thermal process time t is substantially shortened from 1 μsec to 100 msec as compared with spike RTA (the thermal process time t: 50 msec to 1 sec) to thereby suppress the impurity diffusion, and a very high temperature-increasing/decreasing rate Δt of about 1×106° C./sec (note that Δt is 1×107° C./sec or less) is used to thereby allow for a very short process at a high temperature (1000 to 1400° C. in practice). With such a millisecond annealing, it is possible to realize a short thermal process at a higher temperature, thereby reducing the impurity diffusion length while improving the activation rate. Generally, three methods of millisecond annealing have been proposed in the art. The first is a method in which the entire surface of a silicon wafer is heated simultaneously and directly by short-wavelength light near visible light using a flash lamp or an arc lamp as the light source (heat source). The second is a method in which a wafer is heated over a limited zone at a time by a short-wavelength pulsed laser such as an excimer laser, and the heated zone is shifted over time in a step and repeat manner to thereby eventually heat the entire wafer surface. The third is a method in which a wafer and a laser beam in the near infrared to infrared range are moved with respect to each other so as to scan and heat the entire wafer surface. While these millisecond annealing methods may each be used alone as an impurity-activating thermal process method, it is sometimes difficult to form an intended diffusion profile with the impurity diffusion being overly suppressed by millisecond annealing as described above. In view of this, also proposed in the art is a method in which a spike RTA or regular RTA process is performed successively before or after millisecond annealing (see Patent Document 1).    Patent Document 1: Japanese Patent No. 3699946